Publication Date

1988

Document Type

Dissertation/Thesis

First Advisor

Kuo, Sen M. (Sen-Maw)

Degree Name

M.S. (Master of Science)

Legacy Department

Department of Electrical Engineering

LCSH

Multiprocessors; Adaptive filters; Signal processing

Abstract

Many everyday problems encountered in communications and signal processing involve removing noise and distortion due to physical processes that are time varying or unknown or possibly both. These types of processes represent some of the most difficult problems in transmitting and receiving information. Adaptive digital filters present the most effective solution to these problems. In particular, adaptive line enhancer (ALE) provides an efficient means of adaptively tracking the sinusoidal components in a received signal and separates these narrow-band signals from broadband noise. Real-time implementation of Infinite Impulse Response (HR) ALE, Lattice ALE, and Adaptive Frequency Sampling Line Enhancer is done on a TMS32010 digital signal processor from Texas Instruments, and the various issues in the implementation of these filters are discussed in this thesis. These adaptive line enhancers have been shown to be effective in practical applications when there is insufficient a priori knowledge of the signal and noise parameters. Some new application areas for an HR filter are investigated. Many of the signal-processing applications require higher speed and throughput rates. Single processor may not be able to provide sufficient speed and throughput requirements of a particular application. As such, many signal processors are connected together in a multiprocessor environment in order to meet these requirements. Two multiprocessor systems with TMS32010 as the central processing unit are presented. TMS32010 provides only two control pins, namely BIO (Basic I/O) and INT (Interrupt) for I/O interface. The systems presented here use the BIO pin for the external control. Both of these systems have been built with the use of two processors and are completely functional. For the purpose of multiple line enhancement, many HR ALEs can be connected together in cascade or parallel fashion. Implementation of these structures is done on the multiprocessor systems. A comparison of computational complexity, in terms of data memory and program memory locations required and the throughput achieved in the case of each ALE implemented, has been made and presented in this thesis.

Comments

Bibliography: pages [85]-87.

Extent

viii, 153 pages

Language

eng

Publisher

Northern Illinois University

Rights Statement

In Copyright

Rights Statement 2

NIU theses are protected by copyright. They may be viewed from Huskie Commons for any purpose, but reproduction or distribution in any format is prohibited without the written permission of the authors.

Media Type

Text

Download

Share

COinS