Miller, Gerald D. (Professor of electrical engineering)
M.S. (Master of Science)
Department of Electrical Engineering
Computer architecture||Data compression (Computer science)
Compressing a still picture consistent with the DCT based JPEG digital image compression standard consumes a large amount of processing time. When arithmetic coding is incorporated to increase the compression, the processing time also increases considerably. The extended JPEG image compression algorithm’s execution time is critical in several real time digital image processing applications such as video coding, video telephony, etc. DSP processor based software and hardware solutions, for the efficient and fast implementation of the extended JPEG image compression algorithm, are provided in this thesis. The primary objective of this thesis is to reduce the extended JPEG image compression algorithm’s execution time. This is achieved by using a fast 2-D DCT algorithm and the DSP96002’s inherent parallel processing capabilities. The complications involved with the fast 2-D DCT data access and zigzag ordering is simplified by efficiently using the DSP96002’s addressing capabilities. The software solution is built from two modules, one that performs the 2-D DCT and one that performs arithmetic coding. The software solution’s accuracy and correctness is tested using five standard test images. It takes approximately 0.55 seconds to compress/decompress a 256 x 256 pixel monochrome still picture. The average signal to noise ratio obtained for the five test images is 33 dB. The modular software design approach lends itself for execution on a multiple- instruction multiple-data (MIMD) structure. A two- and three-processor parallel pipelined architecture is proposed. A novel data transfer scheme is introduced in the three-processor structure which reduces processor idleness. Both proposed structures utilize master-slave configurations. The master executes the arithmetic coding while the slave computes the DCT. Finally, a common bus multiple-DSP system is discussed. The DSP modules tied to the system bus implement the algorithm in parallel. The extended JPEG image compression algorithm’s execution time on this multiprocessor system is dependent upon the number of modules tied to the bus and the internal module architecture. A simple and static load distribution method to increase the module utilization is presented for this structure. Excellent speedup factors were obtained when the image compression algorithm was implemented on these architectures. The speedup factors varied from 1.45 to 5.11 when the number of processors ranged from two to six. The extended JPEG image compression algorithm’s average execution time for a 256 x 256 pixel monochrome still image varied from 0.61 to 0.12 s.
Ramaswamy, Srinath V., "A study of the JPEG still image compression standard and its implementation on multi-DSP96002 processor based architectures" (1992). Graduate Research Theses & Dissertations. 746.
ix, 157 pages
Northern Illinois University
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