Publication Date

1992

Document Type

Dissertation/Thesis

First Advisor

Hashemian, Reza

Degree Name

M.S. (Master of Science)

Department

Department of Electrical Engineering

LCSH

Metal oxide semiconductors, Complementary||Parallel processing (Electronic computers)

Abstract

This thesis presents a method to use complementary metal-oxidesemiconductor (CMOS) technology to design and simulate a 32-bits high speed parallel adder, using CAD tools such as Mentor Graphics and CALMA (GDS II) systems. The method implemented to design this fast parallel adder is through the use of group increment. The design is carried out for a 32-bit fast parallel adder. The simulation results show an overall circuit delay about 16 ns using CMOS3 technology. This is much faster than carry look-ahead adder which is widely used as adder in a typical arithmetic logic unit (ALU).

Comments

Includes bibliographical references (pages [96]-97)

Extent

ix, 107 pages

Language

eng

Publisher

Northern Illinois University

Rights Statement

In Copyright

Rights Statement 2

NIU theses are protected by copyright. They may be viewed from Huskie Commons for any purpose, but reproduction or distribution in any format is prohibited without the written permission of the authors.

Media Type

Text

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