FPGA-based CORDIC algorithm for fast DSP processing

Author

Urvinder Singh Raina

Alt Title

FPGA based CORDIC algorithm for fast DSP processing

Publication Date

2003

Document Type

Dissertation/Thesis

Degree Name

M.S. (Master of Science)

Legacy Department

Department of Electrical Engineering

LCSH

Field programmable gate arrays; Computer arithmetic and logic units; Signal processing--Digital techniques--Mathematics

Comments

Includes bibliographical references (pages [49]-50).

Recommended Citation

Raina, Urvinder Singh, "FPGA-based CORDIC algorithm for fast DSP processing" (2003). Graduate Research Theses & Dissertations. 3186.
https://huskiecommons.lib.niu.edu/allgraduate-thesesdissertations/3186

Extent

vi, 62 pages

Language

eng

Publisher

Northern Illinois University

Rights Statement

In Copyright

Rights Statement 2

NIU theses are protected by copyright. They may be viewed from Huskie Commons for any purpose, but reproduction or distribution in any format is prohibited without the written permission of the authors.

Media Type

Text