Publication Date


Document Type


First Advisor

Kuo, Sen M. (Sen-Maw)

Degree Name

M.S. (Master of Science)

Legacy Department

Department of Electrical Engineering


Signal processing--Digital techniques; Electric filters; Digital


The purpose of this project was to design and develop an efficient multiprocessor system to implement the Fast Transversal Filter (FTF) using commercially available microprocessors. The system was also designed with some flexibility in it to be able to run other more common signal-processing algorithms, such as the Least Mean Square (LMS) algorithm, efficiently. Due to the nature of the application, powerful and fast digital signal processors (DSPs) were chosen for the design. First, an LMS-based Adaptive Line Enhancer (ALE) and the FTF were implemented on a single DSP. This was a reference point for working on reducing the iteration cycle time of the filters. Next, the algorithms were analyzed, noting sequential characteristics and heavy computational bottlenecks that limited the speed at which the algorithms run. Once decomposed, parallelisms inside of the algorithms could be exploited. Parallelism within the FTF and within its vector computations were the target of speedup efforts. The algorithms and the vectors they operate on were appropriately partitioned to reduce the number of instruction cycles per iteration of the algorithms. The final design was chosen to maximize speedup and minimize interprocessor communication all with the minimum number of processors and simplest control logic. It consists of 2 pairs of digital signal processors, 12 latches, and 24 OR-gates as control logic. A prototype of the system was built using four Motorola DSP56001 fixed-point digital signal processors. The system developed had a speedup factor of nearly 4 over the single processor implementations. The LMS algorithm iteration cycle was reduced from 4M + 15toM + 26 instruction cycles using the new multiprocessor design. Each iteration of the FTF algorithm required 15M + 151 instruction cycles on a single processor and 5.5M + 74 instruction cycles using the devised architecture.


Includes bibliographical references (pages [42]-43)


[viii], 78 pages




Northern Illinois University

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